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MRF89XA
1.0
OVERVIEW
The high-resolution PLL allows:
Microchip's MRF89XA is a fully integrated, half-duplex,
sub-GHz transceiver. This low-power, single chip FSK
and OOK baseband transceiver supports:
? Superheterodyne architecture
? Multi-channel, multi-band synthesizer with Phase
Locked Loop (PLL) for easy RF design
? Power Amplifier (PA)
? Low Noise Amplifier (LNA)
? I/Q two stage down converter mixers
? I/Q demodulator, FSK/OOK
? Baseband filters and amplifiers
The simplified block diagram of the MRF89XA is
illustrated in Figure 1-1 .
The MRF89XA is a good option for low-cost, high-
volume, low data rate ( ≤ 200 kbps), and two-way short
? Usage of multiple channels in any of the bands
? Rapid settling time, which allows for faster
frequency hopping
A communication link in most applications can be
created using a low-cost 12.8 MHz crystal, a SAW filter
and a low-cost microcontroller. The MRF89XA
provides a clock signal for the microcontroller. The
transceiver can be interfaced with many popular
Microchip PIC ? microcontrollers through a 4-wire
Serial Peripheral Interface (SPI), interrupts (IRQ0 and
IRQ1), PLL lock and clock out. The interface between
the microcontroller and MRF89XA (a typical MRF89XA
RF node) is illustrated in Figure 1-2 .
The MRF89XA supports the following digital data
processing features:
? Received Signal Strength Indicator (RSSI)
range wireless applications. This device is a single chip
FSK and OOK transceiver capable of operating in the
863-870 MHz and 902-928 MHz license-free ISM
frequency bands, and the 950-960 MHz frequency
band.
?
?
?
?
Sync word recognition
Packet handling
Interrupt and flags
Different operating Modes (Continuous, Buffer
The low-cost MRF89XA is optimized for very low-power
consumption (3 mA in Receive mode). It incorporates a
baseband modem with data rates up to 200 kbps in FSK
and 32 kbps in OOK. Data handling features include a
64-byte FIFO, packet handling, automatic CRC
generation and data whitening. The device also
supports Manchester coding techniques. Its highly
integrated architecture allows for minimum external
component count while maintaining design flexibility. All
major RF communication parameters are
programmable and most of them may be dynamically
set.
The MRF89XA supports a stable sensitivity and
linearity characteristics for a wide supply range and is
internally regulated. The frequency synthesizer of the
MRF89XA is a fully integrated integer-N type PLL. The
oscillator circuit provided on the MRF89XA device
provides the reference clock for the PLL. The
frequency synthesizer requires only five external
components which includes PLL loop filter and the
VCO tank circuit. Low-phase noise provides for
excellent adjacent channel rejection capability, Bit Error
Rate (BER) and longer communication range.
and Packet)
? Data filtering/whitening/encoding
? Baseband power amplifier
? 64-byte TX/RX FIFO
The role of the digital processing unit is to interface the
data to/from the modulator/demodulator and the
microcontroller access points (SPI, IRQ and DATA pins).
It also controls all of the Configuration registers. The
receiver's Baseband Bandwidth (BBBW) can be
programmed to accommodate various deviations and
data rates requirements.
An optional Bit Synchronizer (BitSync) is provided, to
supply a synchronous clock and data stream to a
companion microcontroller in Continuous mode, or to
fill the FIFO with glitch-free data in Buffered mode. The
transceiver is integrated with different power-saving
modes and a software wake-up time through the host
microcontroller to keep track of the activities, which
reduces the overall current consumption and extends
the battery life. The small size and low-power
consumption of the MRF89XA makes it ideal for
various short range radio applications.
The MRF89XA complies with European (ETSI EN 300-
220) and United States (FCC Part 15.247 and 15.249)
regulatory standards.
? 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 7
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